It is known that array memory cells of the flip-flop type can be written into in a reduced time, for a given applied cell writing current, if the potential available to the cell is diminished while writing is in progress. U.S. Pat. No. 3,813,653 for "Memory Cell With Reduced Voltage Supply While Writing", issued to John L. Smith et al. on May 28, 1974 and U.S. Pat. No. 3,971,004 for "Memory Cell With Decoupled Supply Voltage While Writing", issued to Andrew Dingwall on July 20, 1976 are two examples of the aforementioned technique. In each case, the cell voltage supply circuit is complicated somewhat to provide for the desired potential control action.
Some memory array applications, especially those having closely associated large scale integrated logic circuits, make it advantageous to power both the array and the logic circuits from the same constant voltage sources. Accordingly, it is desirable that enhanced memory cell writing be accomplished while permitting the application of constant voltages to each cell.